1. Field of the Invention
The present invention relates to semiconductor integrated circuit manufacturing and, more particularly to a method of forming a conformal dielectric film such as a silicon nitride film.
2. Description of the Related Art
Integrated circuits fabricated on semiconductor substrates for large scale integration require multiple levels of metal interconnections to electrically interconnect discrete layers of semiconductor devices formed on semiconductor chips. The different levels of interconnections are separated by various insulating or dielectric layers, which are etched to form via holes so as to connect one level of metal to another.
The evolution of chip design continually requires faster circuitry and greater circuit density than before. For faster circuits with greater circuit densities, certain properties are required of materials used to fabricate such integrated circuits, particularly as the dimensions of integrated circuit components are reduced to the sub-micron scale. Also, for greater integrated circuit densities, certain process sequences are required for the manufacture of integrated circuit components.
In recent years, silicon nitride layers deposited at low temperatures (less than 400° C) have been used in a number of important applications for memory devices, for example, as a passivation layer, a surface protection layer and/or a spacer for a transistor gate. Silicon nitride films may be formed by a plasma enhanced chemical vapor deposition (PECVD) method. The main advantages of the PECVD method over other CVD methods are higher deposition rates, and the controllability over a wide range of refractive indices. A further advantage of the PECVD method is that the process can take place at a relatively low temperature, for example temperatures under 400° C, keeping the total thermal budget of the cell processing to a minimum.
However, the PECVD method for forming silicon nitride leads to poor conformality or poor step coverage on a substrate containing small and/or high aspect ratio features. In small circuits and devices, such as ultra-large scale integrated (ULSI) circuitry, poor conformal coverage can hamper the development of higher density circuit devices and elements.